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INTEGRATED CIRCUITS
DATA SHEET
SAA7707H Car radio Digital Signal Processor (CDSP)
Preliminary specification Supersedes data of 1996 May 22 File under Integrated Circuits, IC01 1997 May 30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
CONTENTS 1 1.1 1.2 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 FEATURES Hardware Software APPLICATIONS GENERAL DESCRIPTION QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION Signal path for level information Level ADC switch mode integrator (pin CINT) Internal ground reference for the level ADC (pin VDACNL) Common mode reference voltage for RDS ADC, ADC level and buffers (pin VrefRDS) Signal path for audio/MPX and stereo decoder Mono/stereo switching The automatic lock system Input sensitivity for FM Common mode reference voltage for MPX ADC and buffers (pin VrefMPX) Supply voltages for the switch capacitor DACs of the FMMPX ADC and FMRDS ADC (pins VDACNM and VDACPM) Noise level TAPE/AUX de-multiplex Signal-to-noise considerations Channel separation correction Input selection switches Analog inputs supply Digitally controlled sampling clock (DCS) Survey of the DCS clock settings in different modes Synchronization with the core Interference absorption circuit IAC testing ANALOG OUTPUTS Digital-to-Analog Converters Upsample filter Volume control Power-on mute Power-off plop suppression Internal reference buffer amplifier of the DAC (pin Vref) Internal DAC current reference Analog outputs supply 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 11 12 13 14 15 15.1 15.2 15.3 15.4 15.5 15.6 16 17 18 19 19.1 19.2 19.3 19.4 20 21 22 9.9 9.10 9.11 10 10.1 10.2 10.3 10.4 Clock circuit and oscillator Crystal oscillator supply External control pins I2S-BUS DESCRIPTION
SAA7707H
I2C-bus control (SCL and SDA pins) I2S-bus description Communication with external digital audio sources (DCC + CD-WS/CL/Data pins) Communication with external processors and other devices (EXWS/CL/EXDAT1 and EXDAT2) Relationship between external input and external output RDS decoder (RDSCLK and RDSDAT) Clock and data recovery Timing of clock and data signals Buffering of RDS data Buffer interface DSP reset Power supply connection and EMC LIMITING VALUES THERMAL CHARACTERISTICS DC CHARACTERISTICS AC CHARACTERISTICS I2C-BUS CONTROL AND COMMANDS Characteristics of the I2C-bus Bit transfer START and STOP conditions Data transfer Acknowledge I2C-bus format SOFTWARE DESCRIPTION APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction Reflow soldering Wave soldering Repairing soldered joints DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
8.11 8.12 8.13 8.14 8.15 8.16 8.17 8.18 8.19 8.20 8.21 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
1 1.1 FEATURES Hardware 2 APPLICATIONS
SAA7707H
* Car radio * Car audio systems. 3 GENERAL DESCRIPTION
* Bitstream 3rd-order Sigma-Delta Analog-to-Digital Converters (ADCs) with anti-aliasing broadband input filters * Digital-to-Analog Converters (DACs)with four times oversampling and noise shaping * Digital stereo decoder * Improved digital Interference Absorption Circuit (IAC) * RDS processing with optional 16-bit buffer via separate channel (two-tuner radio possible) * Auxiliary analog CD input (CD-walkman, speech, economic CD-changer, etc.) * Two separate full I2S-bus CD and DCC high performance interfaces * Expandable with additional Digital Signal Processors (DSPs) for sophisticated features through an I2S-bus gateway * Audio output short-circuit protected * I2C-bus controlled * Analog tape input * Operating ambient temperature from -40 to +85 C. 1.2 Software
The SAA7707H performs all the signal functions in front of the power amplifiers and behind the AM and FMMPX demodulation of a car radio or the tape input. These functions are: * Interference absorption * Stereo decoding * RDS decoding * FM and AM weak signal processing (soft mute, sliding stereo, etc.) * Dolby-B tape noise reduction * The audio controls (volume, balance, fader, tone and dynamics compression). Some functions have been implemented in hardware (stereo decoder, RDS decoder and IAC) and are not freely programmable. Digital audio signals from external sources with I2S-bus formats are accepted. There are four independent analog output channels. This enables, in special system configurations, separate tone and equalization control for front and rear speakers. The CDSP contains a basic program that enables a set with: * AM/FM reception * Sophisticated FM weak signal functions * Music Search detection for Tape (MSS) * Dolby-B tape noise reduction system * CD play with compressor function * Separate bass and treble tone control and fader/balance control. For high-end sets with special and more sophisticated features, an additional Digital Signal Processor (DSP) can be connected. Examples of such features are: * Noise-dependent volume control * 10-band graphic equalizer * Audio spectrum analyzer on display * Signal delay for concert hall effects.
* Improved FM weak signal processing * Integrated 19 kHz MPX filter and de-emphasis * Electronic adjustments: FM/AM level, FM channel separation and Dolby level * Baseband audio processing (treble, bass, balance, fader and volume) * Dynamic loudness or bass boost * Stereo one-band parametric equalizer * Audio level meter for an automatic leveller (in combination with microcontroller) * Tape equalization (DCC analog playback) * Music Search detection for Tape (MSS) * Pause detection for RDS updates * Dolby-B tape noise reduction * Adjustable dynamics compressor * CD and DCC de-emphasis processing * Signal level, noise and multi-path detection for RDS (I2C-bus command) * Improved AM reception.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
4 QUICK REFERENCE DATA SYMBOL VDDD(tot) IDDD(tot) Ptot S/N PARAMETER total DC supply voltage total DC supply current total power dissipation level ADC signal-to-noise ratio CONDITIONS all supply pins maximum activity of the DSP; fxtal = 36 MHz maximum activity of the DSP; fxtal = 36 MHz RMS value; unweighted; B = 0 to 29 kHz; maximum input not multiplexed; B = 19 kHz; Vi = 1 V (RMS) multiplexed; unweighted; B = 19 kHz; 1 V (RMS) ADC signal-to-noise ratio for FM-RDS ViFS THD Vimc(rms) ADC full-scale input voltage total harmonic distortion pins 62 and 71 to 75 maximum conversion input voltage level pins 62 and 71 to 75 (RMS value) DAC resolution - - 48 MIN. 4.75 5 160 0.8 54 TYP.
SAA7707H
MAX. 5.5 200 1.1 -
UNIT V mA W dB
ADC signal-to-noise ratio
81
85
-
dB
72
76
-
dB
RMS value; B = 6 kHz; 56 unweighted; fc = 57 kHz VDDA1 = 4.75 to 5.5 V fi = 1 kHz; Vi = 1 V (RMS) THD < 1% 1.05VDDA1 - - 1.1
- 1.1VDDA1 -71 0.03 -
- 1.15VDDA1 -61 0.09 -
dB V dB % V
RES (THD + N)/S
-
18 -70
- -60
bits dB
total harmonic distortion plus RL > 5 k AC; - noise-to-signal ratio for DAC Rfb = 2.7 k; fi = 1 kHz; and operational amplifiers Rref = 18 k; VoFS = 2.8 V (p-p); maximum I2S-bus signal dynamic range of DAC digital silence of DAC crystal frequency DSP part fi = 1 kHz; -60 dB; A-weighted fi = 20 Hz to 17 kHz; A-weighted 92 - -
DR DS fxtalDSP 5
102 -110 36.86
- -100 -
dB dB MHz
ORDERING INFORMATION TYPE NUMBER PACKAGE NAME QFP80 DESCRIPTION plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 29 x 2.8 mm VERSION SOT318-2
SAA7707H
1997 May 30
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CINT 77 78 70 80 62 4 3 72 74 73 71 75 76 79 ADC ANALOG SOURCE SELECTOR ADC INTERFERENCE ABSORPTION CIRCUIT DIGITAL STEREO DECODER DIGITAL SIGNAL PROCESSOR DIGITAL SOURCE SELECTOR QUADRATURE DAC 11 12 9 10 21 RDS DECODER CRYSTAL OSCILLATOR DIGITALLY CONTROLLED SAMPLING 25 48 47 46 59 57 58 35 36 28 27 37 I2C-BUS INTERFACE RIOL RVOL RIOR RVOR POM SIGNAL QUALITY ADC SIGNAL LEVEL 2 VDACNL VSSG VSSA1 1 67 68 VSSD2 VSSD1 5 VSSD3 VSSD4 22 50 51 VSSD5 VDDD3 VSSD8 VDDD4 VSSD6 VSSD9 VSSD7 VDDD2 VDDD5 54 55 34 41 29 56 49 52 53 VSSO VDDD1 MSS/P MUTE VDDA VDDO V DEEM SSA VDDA1 VSSD1 STEREO 44 45 42 43 8 69 15 14 6 5 7 40 20 13 18 19 16 17 EXCLK Vref Iref(int) FIOL FVOL FIOR FVOR VDACPM VDACNM VrefMPX VrefRDS MPXRDS AM FM AUXR TAPER TAPEL AUXL AMAF FMMPX FMRDS
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Philips Semiconductors
Car radio Digital Signal Processor (CDSP)
BLOCK DIAGRAM
SAA7707H
Fig.1 Block diagram.
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5
32 33 30
66 65
60
61
64 XTALO
63 23 24
38 39 31 26
MBH163
TSCAN VDDX SHTCB VSSX RTCB
RDSDAT RDSCLK
TEST1 CDWS DCCWS EXSCL DCCDAT EXDAT CDCLK TEST2 DCCCLK CDDAT XTALI VSSD10
EXWS EXDAT1 EXDAT2
A0 SDA DSPRESET SCL
Preliminary specification
SAA7707H
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
7 PINNING SYMBOL VDACNL CINT FM PIN 1 2 3 I I/O - DESCRIPTION internal ground reference voltage for the level ADC level ADC switch-mode integrator connector
SAA7707H
FM level input; via this pin, the level of the received FM radio signal is fed to the CDSP, the level information is required to enable correct functioning of the weak signal behaviour AM level input; via this pin, the level of the received AM radio signal is fed to the CDSP ground supply 1 for the DACs digital circuitry ground supply for the DACs analog circuitry positive supply 1 for the DACs digital circuitry positive supply for the DACs analog circuitry analog audio current output for rear right speaker analog audio voltage output for rear right speaker analog audio current output for rear left speaker analog audio voltage output for rear left speaker internal reference current source input for the DACs ground supply for DAC output operational amplifiers positive supply for DAC output operational amplifiers analog audio current output for front right speaker analog audio voltage output for front right speaker analog audio current output for front left speaker analog audio voltage output for front left speaker voltage input for the internal reference buffer amplifier of the DAC activates the Power-on mute; timing is determined with an external capacitor ground supply 2 for the digital circuitry clock input for CD digital audio source (I2S-bus) Word Select input for CD digital audio source (I2S-bus) left/right data input for CD digital audio source (I2S-bus) input to reset DSP core (active LOW) external input data channel 1 (front) from extra DSP chip (I2S-bus) external input data channel 2 (rear) from extra DSP chip (I2S-bus) ground supply 9 for the digital circuitry scan control (active HIGH) I2S-bus selection for slave sub-address asynchronous reset test control block (active HIGH) shift clock test control block (active HIGH)
AM VSSD1 VSSA VDDD1 VDDA RIOR RVOR RIOL RVOL Iref(int) VSSO VDDO FIOR FVOR FIOL FVOL Vref POM VSSD2 CDCLK CDWS CDDAT DSPRESET EXDAT1 EXDAT2 VSSD9 TSCAN A0 RTCB SHTCB VSSD7 EXDAT EXSCL EXWS
4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37
I - - - - O O O O I - - O O O O I - I I I I I I -
- O O I/O
ground supply 7 for the digital circuitry output data for extra external DSP chip (I2S-bus) output clock for extra external DSP chip (I2S-bus) word select input/output for extra external DSP chip (I2S-bus)
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL SCL SDA EXCLK VSSD8 STEREO MSS/P MUTE DEEM DCCCLK DCCWS DCCDAT VDDD3 VSSD3 VSSD4 VDDD4 VDDD5 VSSD5 VSSD6 VDDD2 TEST1 VSSD10 TEST2 RDSCLK RDSDAT MPXRDS XTALI XTALO VDDX VSSX VSSG VSSA1 VDDA1 VrefMPX AUXL AUXR TAPEL TAPER AMAF FMMPX 1997 May 30
PIN 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
I/O I I/O I - serial clock input (I2C-bus)
DESCRIPTION serial data input/output (I2C-bus) external reference clock input to generate 4fas and fas synchronization; to be used if the I2S-bus inputs are not suitable ground supply 8 for the digital circuitry FM stereo indication (active HIGH) FM pause detector/MSS detector (active HIGH); also for IAC trigger output
I I I I - - - - - - - - - I/O O I I O - - - - - I I I I I I I
MUTE input pin (active LOW); only for FM mode de-emphasis; CD and DCC (active HIGH) (I2S-bus) DCC digital audio source clock input (I2S-bus) DCC digital audio source Word Select input (I2S-bus) DCC digital audio source left/right data input (I2S-bus) positive supply 3 for the digital circuitry ground supply 3 for the digital circuitry ground supply 4 for the digital circuitry positive supply 4 for the digital circuitry positive supply 5 for the digital circuitry ground supply 5 for the digital circuitry ground supply 6 for the digital circuitry positive supply 2 for the digital circuitry test pin 1 (this pin should be left open-circuit) ground supply 10 for the digital circuitry test pin 2 (this pin should be left open-circuit) radio data system bit clock input/output radio data system data output in FM mode, selects between FMMPX and RDSMPX input signal to the MPX decimation filter crystal oscillator input; can also be used as forced input in slave mode crystal oscillator output positive supply crystal circuitry ground supply crystal circuitry ground guards for ADCs analog ground supply for ADCs analog positive supply for ADCs common mode reference voltage input for MPX ADC and buffers analog input for auxiliary left signal analog input for auxiliary right signal analog input for tape left signal analog input for tape right signal analog input for AM audio frequency analog input for FM multiplex signal 7
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL VDACPM VDACNM FMRDS VrefRDS
PIN 77 78 79 80
I/O I I I I
DESCRIPTION supply voltage for the DACs switch capacitor of the FMMPX ADC and FMRDS ADC ground supply for the DACs switch capacitor of the FMMPX ADC and FMRDS ADC analog FMMPX input for RDS decoding common mode reference voltage input for RDS ADC, level ADC and buffers
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
78 VDACNM
77 VDACPM
70 VrefMPX
80 VrefRDS
76 FMMPX
79 FMRDS
69 VDDA1
74 TAPER
68 VSSA1
73 TAPEL
67 VSSG
75 AMAF
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VDACNL CINT FM AM VSSD1 VSSA VDDD1 VDDA RIOR
65 VDDX 64 XTALO 63 XTALI 62 MPXRDS 61 RDSDAT 60 RDSCLK 59 TEST2 58 VSSD10 57 TEST1 56 VDDD2 55 VSSD6 54 VSSD5 53 VDDD5 52 VDDD4 51 VSSD4 50 VSSD3 49 VDDD3 48 DCCDAT 47 DCCWS 46 DCCCLK 45 DEEM 44 MUTE 43 MSS/P 42 STEREO 41 VSSD8 EXCLK 40
MBH162
72 AUXR
1 2 3 4 5 6 7 8 9
RVOR 10 RIOL 11 RVOL 12
SAA7707H
Iref(int) 13 VSSO 14 VDDO 15 FIOR 16 FVOR 17 FIOL 18 FVOL 19 Vref 20 POM 21 VSSD2 22 CDCLK 23 CDWS 24 CDDAT 25 DSPRESET 26 EXDAT1 27 EXDAT2 28 VSSD9 29 TSCAN 30 A0 31 RTCB 32 SHTCB 33 VSSD7 34 EXDAT 35 EXSCL 36 EXWS 37 SCL 38 SDA 39
Fig.2 Pin configuration.
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66 VSSX
71 AUXL
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8 8.1 FUNCTIONAL DESCRIPTION Signal path for level information
SAA7707H
An FM and AM level input is implemented for FM weak signal processing [for AM, FM and RDS search purposes (absolute level and multi-path)]. A DC input signal is converted by a bitstream 1st-order Sigma-Delta analog-to-digital converter and then filtered by a decimation filter. The input signal has to be obtained from the radio part. Two different circuits for AM and FM reception are possible: 1. A circuit with two separate input signals, one for FM level and one for AM level 2. A combined circuit with AM and FM level information on the FM level input. The AM level input can then be connected to another signal, which can be converted in the non-radio mode. The input is selected via the input selector control register. The input signal for level control must be in the range of 0 to 5 V. The 11-bit level ADC converts this input voltage in steps with a resolution better than 10 mV over the 5 V range. The tolerance on the gain is less than 10%. The MSB is always logic 0, to represent a positive level.
The decimation filter reduces the bandwidth of the incoming signal to a frequency range of 0 to 29 kHz, with a resulting sampling frequency (fs) of 76 kHz. The response curve is illustrated in Fig.3. The level information is sub-sampled by the DSP core to obtain a field strength and a multi-path indication. These values are stored in the coefficient or data RAM. They can be read and used in other microcontroller programs via the I2C-bus. 8.2 Level ADC switch mode integrator (pin CINT)
The level ADC has an internal current summation point of the input level and the switch capacitor DAC. When used as an integrator, an external capacitor of 1000 pF should be connected between this pin and the analog ground at pin VSSA1. The summation voltage is used as an input for the analog-to-digital comparator level. 8.3 Internal ground reference for the level ADC (pin VDACNL)
This pin serves as the internal ground reference for the switch capacitor DAC and the level ADC and has to be connected to the analog ground (pin VSSA1).
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MBH164
(dB) 0
-10
-20
-30
-40
-50
-60
0
10
20
30
40
50
60
70
f (kHz)
80
Fig.3 Frequency response of the level ADC and decimation filter.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.4 Common mode reference voltage for RDS ADC, ADC level and buffers (pin VrefRDS)
SAA7707H
The middle reference voltage of the RDS ADC can be filtered via this pin. This middle reference voltage is used as a positive reference for the level ADC of the switch capacitor DAC and as half supply reference for the RDS ADC, the switch capacitor DACs and buffers. An external capacitor (connected to VSSA1) prevents crosstalk between the switch capacitor DACs of the RDS ADC, level ADC and buffers, and improves the power supply rejection ratio. 8.5 Signal path for audio/MPX and stereo decoder
* `Left' and `Right': This is the 18-bit output of the stereo decoder after the matrix decoding. For AM reception, the `Right' signal contains the AM-mono signal. For tape or auxiliary signals, the output of the stereo decoder contains sum and difference signals, but with other crosstalk properties than on FM. Therefore, a different matrix correction, as shown in Table 1, has to be applied to these signals in the DSP program. The overall frequency response of the demultiplexed signal at the output of the stereo decoder is illustrated in Fig.5. Table 1 Overview of the signals to the CDSP LEFT 0
1 1 2(R
MODE AM FM TAPE/AUX
RIGHT mono R+L R+L
The SAA7707H has four analog audio source inputs; two single-multiplex channel inputs for AM and FM radio and two stereo inputs for tape and auxiliary. The auxiliary input can be used for functions such as an analog CD changer or speech applications. The stereo inputs are multiplexed so that they can share the same filters as the multiplexed FM signal. The selection between the AM, FM, TAPE and AUX input is made via the input selector control register. The input signal behind the source selector is digitized by a bitstream 3rd-order Sigma-Delta ADC. The first decimation filter reduces the sample rate. This is followed by the sample-and-hold switch of the IAC and the 19 kHz regeneration circuit. From here, the wide-band noise detector signal HP2 (High-Pass 2) with a frequency range of 60 to 240 kHz is derived. A second decimation filter reduces the output of the IAC to a lower sample rate. This filter has two outputs, one for the multiplex signal with a frequency range of 0 to 60 kHz (low-pass) and one for the small-band noise detector signal HP1 (High-Pass 1) with a frequency range of 60 to 120 kHz. The overall low-pass frequency response of the decimation filters is illustrated in Fig.4. In the FM mode, the RDS ADC can be used as an input for the MPX decimation filter. This can be selected via the RDSMPX input at pin 62. The outputs from this signal path to the DSP, which are all at a sample frequency of 38 kHz, are as follows: * Pilot presence indication: Pilot-I. This 1-bit signal is LOW for a pilot frequency deviation of less than 4 kHz and HIGH for a pilot frequency deviation greater than 4 kHz. It is AND locked on a pilot tone. * Pilot quality indication: Pilot-Q. This 10-bit signal contains information about the signal quality and is derived from the quadrature component of the pilot-I signal.
- L)
2(R + L) x 4/
Apart from the aforementioned theoretical response, the non-flat frequency response of the ADC must also be compensated for in the DSP program. 8.6 Mono/stereo switching
After division, the Digitally Controlled Sampling (DCS) clock generates a clock signal with a frequency which is a multiple of 19 kHz plus or minus a few Hertz. For mono reception, the DCS circuit generates a preset frequency of n x 19 kHz 2 Hz. For stereo reception, the frequency is exactly n x 19 kHz (DCS locked to n x pilot tone). The detection of the pilot and the stereo indication is performed in the DSP program. 8.7 The automatic lock system
The VCO operates at 19 kHz 2 Hz exactly for no-pilot. For stereo reception, the phase error is zero for a pilot tone with a frequency of exactly 19 kHz. Therefore, no switch is required to preset the clock to 19 kHz. With auxiliary sources (tape, CD, etc.), the DCS circuit has to be preset to a fixed value. 8.8 Input sensitivity for FM
The FM input sensitivity is optimally designed for an FM front-end with an output voltage of 200 mV (RMS) at a modulation depth of 22.5 kHz of a 1 kHz tone. Due to the full-scale 1.2 V (RMS) handling capacity of the ADC, the maximum allowed modulation depth of a transmitter, for a THD of 10%, is 135 kHz. Full performance is possible for transmitters with a modulation depth of up to 110 kHz.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
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10
MBH165
0
-10
(dB) -30 -50 -70 -90 -110 -130 -150 0 50 100 150 200 250 300 350 400 450 f (kHz) 500
Fig.4 Overall frequency response multiplex ADC and decimation filters.
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MBH166
(dB) 0
-20
-40
-60
-80
-100 0 10 20 30 40 50 60 70 f (kHz) 80
Fig.5 Transfer of MPX signal at the output of the stereo decoder.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.9 Common mode reference voltage for MPX ADC and buffers (pin VrefMPX) 8.11 Noise level
SAA7707H
The middle reference voltage of the MPX ADC can be filtered via this pin. This middle reference voltage is used as a half supply voltage reference for the MPX ADC, switch capacitor DACs and buffers. An external capacitor (connected to VSSA1) prevents crosstalk between the switch capacitor DACs and buffers and improves the power supply rejection ratio. 8.10 Supply voltages for the switch capacitor DACs of the FMMPX ADC and FMRDS ADC (pins VDACNM and VDACPM)
The High-Pass 1 (HP1 or narrow-band noise level filter) output of the second MPX decimation filter, in a frequency band from 60 to 120 kHz, is detected with an envelope detector and decimated to a frequency of 38 kHz. The response time of the detector is 100 ms. Another option is the High-Pass 2 (HP2 or wide-band noise level filter). This output from the first MPX decimation filter is in a frequency band from 60 to 240 kHz. It has the same properties as the HP1 and is also decimated to 38 kHz. Which signal is used (HP1 or HP2) is determined by the input selector control register. The noise level can be detected and filtered in the DSP core and can be used to optimize the FM weak-signal processing. The transfer curves of both filters before decimation are illustrated in Fig.6.
These pins are used as ground and positive supply voltage reference for the MPX ADC, RDS ADC and the switch capacitor DACs. For optimum performance they must be connected directly to VSSA1 and VDDA1.
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10 0
MBH167
-10
(dB) -30 -50 -70 -90 -110 -130 -150 0 50 100 150 200 250 300 f (kHz) 350 (2) (1)
(1) Narrow-band noise level filter. (2) Wide-band noise level filter.
Fig.6 Frequency response of noise level before decimation.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.12 TAPE/AUX de-multiplex Table 2 Analog input selection
SAA7707H
The auxiliary and tape inputs also use the stereo decoder. Because of this, the left and right channels are multiplexed with a 38 kHz square wave to obtain a signal similar to the FM multiplexed signal. Auxiliary inputs can be e.g. TV-sound, remote players (tape deck, CD-changer with analog output etc.). The signal-to-noise ratio from such sources is limited by the ADC in the SAA7707H (>75 dB). The decimation filter of the ADC attenuates the harmonic signals from this stereo encoder. For an optimum channel separation, the 38 kHz switch signal has to be phase corrected to compensate for the delay of the ADC and decimation filters. This can be adjusted with the 3-bit group delay compensation in the IAC control register. Signal frequencies above 19 kHz at the input of the multiplexer are converted to the audio base-band and are therefore not allowed. 8.13 Signal-to-noise considerations
I2C-BUS SELECTION BIT AM/FM 0 1 x x 8.16
SWITCH
AUX/ TAPE/ SFM SAM SAUX SAUX RADIO AUX 0 0 1 1 x x 0 1 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1
Analog inputs supply
The analog input circuit has its own separate power supply connections to allow maximum filtering. These pins are VSSA1 for the analog ground and VDDA1 for the analog power supply. VSSG is the connection to the guard ring which isolates the analog part from the digital filters. This pin has to be connected to the analog ground. 8.17 Digitally controlled sampling clock (DCS)
Due to the pre-emphasis of FM broadcasts, the theoretical signal-to-noise ratio is approximately 3 dB higher for FM stereo in comparison with multiplexed inputs. To avoid aliasing into the tape channel, the tape noise from the pre-amplifier must be attenuated before analog-to-digital conversion with a 1st-order 10 kHz low-pass filter. The frequency response is equalized after the stereo decoder in the DSP program before the Dolby decoder software. Using this filter, the signal-to-noise ratio of this channel is degraded by 3 dB. This results in a signal-to-noise ratio that is overall 6 dB lower than a tape input with respect to FM stereo. 8.14 Channel separation correction
The crystal clock generates a continuous clock signal for the internal DSP core. In the radio mode, the stereo decoder, the RDS decoder, the ADCs and the level decimation filters have to run synchronously with the 19 kHz pilot. Therefore, a clock signal with a controlled frequency with a multiple of 19 kHz (9.728 MHz = 512 x 19 kHz) is required. In the SAA7707H, the patented method of a non-continuous digitally controlled sampling clock has been implemented. A frequency of 9.728 MHz is generated by a special dividing mechanism of the master crystal clock. Since the dividing mechanism is fixed, only a crystal frequency of 36.86 MHz can be used. The DCS system is controlled by up/down information from the stereo decoder. For mono transmissions, the DCS clock is still controlled by the stereo decoder loop. The output keeps the DCS free-running at a multiple frequency of 19 kHz 2 Hz. In TAPE/AUX and AM mode, the DCS clock must always be put in preset mode by the input selector control register.
The channel separation is approximately 50 dB at 1 kHz and 35 dB at 15 kHz. Because the frequency response of the ADC has some deviation from the flat curve around 38 kHz, a perfect channel separation cannot be obtained. Therefore, the de-multiplexed signal is corrected for crosstalk in the DSP program. 8.15 Input selection switches
A schematic diagram of the input selection is illustrated in Fig.5. The input selection is controlled by bits in the input selector control register. The relationship between these bits and the switches is indicated in Table 2.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
8.18 Survey of the DCS clock settings in different modes 8.20
SAA7707H
Interference absorption circuit
The DCS clock behaves as shown in Table 3. Table 3 DCS clock/mode MODE FM stereo FM mono AM analog inputs TAPE/AUX I2C-bus inputs DCC/CD 8.19 DCS CLOCK locked on 19 kHz pilot of received FM signal free running fixed preset fixed preset
The Interference Absorption Circuit (IAC) detects and suppresses ignition interference. This hardware IAC is a modified and digital version of the analog circuit that has already been in use for many years. The input signal to the IAC circuit is derived from the output signal of the decimation filter. The interference detector analyses the high frequency content of this MPX signal. The discrimination between interference pulses and other signals is performed by a special Philips patented fuzzy logic-like algorithm and is based on probability calculations. This logic will send appropriate pulses to an MPX mute switch. At Power-on, the nominal setting for an IAC with good performance characteristics is selected (all IAC control bits are 0). If an adjustment is needed, the characteristics can be adapted as described in the application manual. 8.21 IAC testing
Synchronization with the core
A 38 kHz synchronization signal is derived from the DCS clock and divided by 256. If the external I2S-bus DCC CD is selected, the rising edge of the Word Select input signal is used to synchronize with the core.
The internal IAC trigger signal is visible on the MSS/P pin (pin 43) if the IAC trigger output bit of the IAC control register is set. In this mode, the effect of the parameter settings on the IAC performance can be verified.
1997 May 30
15
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
0
handbook, full pagewidth
FM AM 1 0 TAPER 1
SAMFM ADC level
0 STAPE 0 1
CLMPX ADC
TAPEL 1 0 AUXR 1 SAUX 0 AUXL 1 0 AM/FM 1 0 FMMPX 1 SFM 0 SAM 0 1 RDS_MPX MPX
1 0 FMRDS 1 SINTEXT ADC
MBH168
RDS
Fig.7 Schematic diagram of input selection. * The SAMFM switch is controlled by the SEL-LEV-AM/FM bit * The SINTEXT switch is controlled by the SEL-RDS-EXT/INT bit * The CLMPX switch is controlled by the 38 kHz clock derived from the DCS, but is not active in FM and AM mode. In the FM radio mode, the MPXRDS pin overrides the following switches when set to logic HIGH: If SEL-AM/FM = 0 and SEL-AUX/RADIO = 0 and pin MPXRDS = 1, then SFM = 0, SINTEXT = 1 and MPXRDS = 1.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
9 9.1 ANALOG OUTPUTS Digital-to-analog converters
SAA7707H
Each of the four low-noise high dynamic range DACs consists of a 15-bit signed magnitude DAC with current output, followed by a buffer operational amplifier. The five higher bits (bits 10 to 14) are used to control the total coarse current ratio of the 32 coarse current sources via a thermometer decoder. The nine lower bits (bits 1 to 9) are derived from a 512 transistor matrix, which acts as a passive 9-bit current divider for one of the coarse currents. The MSB (bit 15) is used as a sign bit for the signed magnitude converter and controls the direction of the total output current. A separate converter is used for each of the four audio output channels. The value of each coarse current is adjusted by the current through the external resistor connected to pin 13 (Iref(int)). Each converter output is connected to the inverting input of one of the four internal CMOS operational amplifiers. The non-inverting input of this operational amplifier is connected to the internal reference voltage. Together with an external resistor, the current-to-audio output voltage conversion is achieved. 9.2 Upsample filter
For external digital sources (DCC and CD), a sample frequency from 32 to 48 kHz is possible. The sample frequency is automatically adjusted to the I2S-bus input by dividing the external bit clock. This clock is normally present in a DCC CD application. An internal digital PLL divides this clock with the integer factor needed to obtain the 4fas word clock. Master synchronization of this divided clock signal is obtained with a reset of the divider on the Word Select signal (trailing edge) of the I2S-bus. In the application, the I2S-bus signal from the external source should fulfil the following requirements: * There is a continuous (is part of the basic I2S-bus specification) n x 4fas (4 < n < 128) I2S-bus bit clock or * If the I2S-bus bit clock is not continuous, another n x 4fas (4 < n < 128) continuous clock signal has to be connected to the EXCLK pin (pin 40). The divide external clock mode has to be selected using the input selector control register. The range of the internal 7-stage programmable divider of the PLL, to obtain 4fas, is large enough to handle 16-bit I2S-bus signals as well as master clocks up to 22 MHz from digital sources (CD, DCC, R-DAT and EBU interface) without any clock regeneration. The PLL is used in a free-running mode to ensure that jitter on the I2S-bus signals (due to asynchronous clocking of the I2S-bus signals by the DSP core) will not influence the total harmonic distortion of the audio signal on the analog DAC part. This will, however, only operate if there is no jitter on the bit clock or when a crystal clock is used. 9.3 Volume control
To reduce spectral components above the audio band, a fixed 4 times oversampling and interpolating 18-bit digital IIR filter is used. It is realized as a bit serial design and consists of two consecutive filters. The data path in these filters is 22 bits, to prevent overflow and to maintain a theoretical signal-to-noise ratio greater than 105 dB. The filters give an attenuation of at least 29 dB. The filter is followed by a 5 bit 1st-order noise shaper, to expand the dynamic range to more than 105 dB. The band around multiples of the sample frequency of the DAC (4fas) is not affected by the digital filter. A capacitor can be added in parallel with the output resistor at the DAC output to further attenuate this out-of-band noise to an acceptable level. The overall frequency spectrum at the DAC audio output without external capacitor/low-pass filter for the audio sampling frequencies (fas) of 38 kHz is illustrated in Fig.8. The detailed spectrum around fas is illustrated in Fig.9 for an fas of 38 kHz, 44.1 kHz and 48 kHz. The pass-band bandwidth (at -3 dB) is 12fas. The word clock for the upsample filter (4fas) is derived from the audio source timing. If the internal audio source is selected, the sample frequency is fixed at 38 kHz.
The total volume control has a dynamic range of more than 100 dB. With the signed magnitude noise-shaped 15-bit DAC and the internal 18 bit registers of the DSP core, a useful digital volume control range of 100 dB is possible by calculating the corresponding coefficients. The step size is freely programmable and an additional analog volume control is not needed in this design. The signal-to-noise ratio of the audio output, at full-scale, is determined by the total 15 bits of the converter. The noise at low outputs is fully determined by the noise performance of the DAC. Since it is a signed magnitude type, the noise at digital silence is also low. The disadvantage is that the total THD is higher than conventional DACs. The typical signal and noise levels as a function of the output level and the typical signal-to-noise plus THD as a function of the output level are illustrated in Fig.10.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
9.4 Power-on mute
SAA7707H
To avoid any uncontrolled noise at the audio outputs after Power-on of the IC, the reference current source of the DAC is switched off. The capacitor connected to pin 21 (POM) determines the time after which this current has a soft switch-on. Consequently, at Power-on, the current audio signal outputs are always muted. The voltage output signals will show a small jump at switch-on due to the asymmetrical voltage supply of the output operational amplifiers. These types of disturbances must be eliminated via the application set-up. The output has to be set to digital silence before the POM pin is at logic HIGH. This is achieved via the DSP program control and/or a zero volume setting. The pin is internally connected to VDDO with a high-ohmic resistor. 9.5 Power-off plop suppression
The operational amplifiers have the VSSO and VDDO pins as ground and positive supply. These pins also provide the supply for the reference circuits. The analog DAC part uses the VSSA and VDDA pins as ground and positive supply. The upsample filter and digital part of the DAC share the VSSD1 and VDDD1 as ground and positive supply connections. 9.9 Clock circuit and oscillator
The SAA7707H has an on-board crystal clock oscillator. The schematic of this Pierce oscillator is illustrated in Fig.11. The active element needed to compensate for the loss resistance of the crystal is the block `Gm'. This block is placed between the XTAL (output) and the OSC (sense) pins. The gain of the oscillator is internally controlled by the AGC block; this prevents excessive power loss in the crystal. The higher harmonics are then as low as possible. The signal on the XTAL pin is amplified and divided by two. This 18.43 MHz signal is then used as the DSP clock signal (PH2). For the high frequency, as used in the SAA7707H, normally only third overtone crystals are available. With an external LC notch filter at the fundamental frequency, oscillation at this frequency can be avoided.The crystal frequency is chosen in such a way that the harmonics are outside the normal FM band. The crystal frequency used is 36.86 MHz. 9.10 Crystal oscillator supply
To avoid plops in a power amplifier, the supply voltage of the analog part of the DAC can be fed via a Schottky diode and an extra capacitor. In this situation, the output voltage will decrease gradually, allowing the power amplifier some extra time to switch off without audible plops. 9.6 Internal reference buffer amplifier of the DAC (pin Vref)
Using two internal resistors, half of the supply voltage (VDDO) is obtained and coupled to an internal buffer. This reference voltage is used as a DC voltage for the output operational amplifiers and as a reference voltage for the DAC. In order to obtain the lowest noise and to have the best ripple rejection, a filter capacitor has to be added between this pin and ground. 9.7 Internal DAC current reference
The power supply connections for the oscillator are separate from the other supply lines. This is to minimize the feedback from the ground bounce of the chip to the oscillator circuit. The VSSX pin (pin 66) is used as ground supply and the VDDX pin (pin 65) as positive supply. 9.11 External control pins
As a reference for the current at the DAC current source, a current is drawn from pin 13 (Iref(int)) to the VSSO ground. The voltage at this pin is 12VDDO (typically 2.5 V). The maximum DAC current is equal to 4.5 times this current. When a reference resistor of 18 k is used, the reference current from the DAC is 125 A. This results in a peak current from the four current outputs of 4.5 x 125 = 562.5 A. 9.8 Analog outputs supply
For external control, two input pins have been implemented. The status of these pins can be changed by applying a logic level, and is recorded in the internal status register. The functions of each pin are as follows: * MUTE (pin 44). Mute input (0 = MUTE) * DEEM (pin 45). This pin activates the de-emphasis for CD and DCC. (1 = de-emphasis on). To control external devices, two output pins are implemented. The status of these pins is controlled by the DSP program. The functions of each pin are as follows:
For an optimum signal-to-noise performance, supply ripple rejection and to suppress switch-off plops, the output operational amplifiers, the analog part of the DACs and the upsample filter plus digital part have separate power supply connections.
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
* STEREO (pin 42): Indicates whether an FM broadcast is in stereo (1 = stereo)
SAA7707H
* MSS/P (pin 43): Indicates a pause in FM or tape search mode (1 = pause). This is also the IAC trigger output for IAC alignment if the corresponding I2C-bus bit is set.
handbook, full pagewidth
5
MBH169
0
-5
(dB) -15
-25
-35
-45
-55
-65 0 50 100 150 200 250 300 350 400 450 f (kHz) 500
Fig.8 Overall frequency spectrum audio output (fas = 38 kHz).
handbook, full pagewidth
10
MBH170
(dB) 0
-10
-20
-30
-40
-50 0 0 0 10000 11605 12632 20000 23211 25263 30000 34815 37895 f (Hz) 40000 46420 50528
Fig.9 Detailed frequency spectrum of audio output.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
100
MBH171
S/(N+THD) and S/N (dB) 80
60
(1) 40
(2) 20
0 -100
-90
-80
-70
-60
-50
-40
-30
-20
-10 output level (dB)
0
(1) Signal-to-noise. (2) Signal-to-noise + total harmonic distortion.
Fig.10 Typical signal-to-noise level and signal-to-noise plus THD as a function of output level.
handbook, full pagewidth
AGC
Gm
/2 PH2
ON CHIP OFF CHIP
63 OSC
64 XTAL
65 VDDX
66 VSSX
Rbias Cx1 Cx2
MBH172
Fig.11 Schematic diagram of the oscillator circuit.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
10 I2S-BUS DESCRIPTION 10.1 I2C-bus control (pins SCL and SDA)
SAA7707H
The Word Select line automatically determines the SAA7707H sampling frequency. Using the Digital Source Selector (see Fig.1), one of the three possible input sources is selected. The selected audio data channels are input to two 18-bit wide memory mapped I/O registers of the DSP named Input Left and Input Right. Except for the 4fas pulse to control the upsample filter (see Section 9.2), other synchronization signals such as internal Word Select are derived from the I2S-bus input signals. The input bit clock is used as a bit clock for the external processor. As a consequence, a clock pulse input signal with less than 18 bits will result in a communication with an external processor of the same number of bits. In this event, the trailing bits of the 18-bit input registers will be zero. If the I2S-bus driver outputs of the external digital source ICs have 3-state outputs, they can all be connected on one single I2S-bus input. 10.4 Communication with external processors and other devices (EXWS/CL/EXDAT1 and EXDAT2)
For external control of the SAA7707H, a standard I2C-bus is implemented. There are two different types of control instructions: * Instructions to control the DSP program, programming the coefficient RAM and reading the values of parameters (level, multi-path etc.) * Instructions controlling the DATA flow, such as source selection, IAC control and clock speed. 10.2 I2S-bus description
For communication with external digital sources and/or additional external processors, the I2S-bus digital interface is used. It is a serial 3-line bus, having one line for Serial Data (SD), one line for Serial Clock (SCK) and one line for the Word Select (WS). For external processors, the CDSP acts as a master transmitter; for external digital sources the CDSP acts as a slave. The communication with the external processor and external digital sources are separated, to allow both features at the same time. Figure 12 shows an extract of the Philips I2S-bus specification interface report regarding the general timing and format of the I2S-bus. Word select logic 0 means left channel word; word select logic 1 means right channel word. The serial data is transmitted in twos complement with the MSB first. One clock period after the negative edge of the Word Select line, the MSB of the left channel is transmitted. Data is synchronized with the negative edge of the clock and latched at the positive edge. As inputs from an external processor for the four audio channels, two data lines have been implemented. 10.3 Communication with external digital audio sources (DCC + CD-WS/CL/Data pins)
For communication with external processors, delay lines or other I2S-bus controllable devices, a complete dual-channel 18-bit output bus is implemented. The SAA7707H acts as the master transmitter and the external device has to be synchronized with the Word Select line. As input for the processed data, two data input lines have been implemented that are processed synchronously with the data output to the external processor (see Table 4). This enables, in total, a feedback of two stereo audio channels. For this communication, the DSP core has the following 18-bit memory mapped I/O registers available: Table 4 DSP core I/O registers INPUT EXDAT1 left/right EXDAT2 left/right OUTPUT EXDAT left/right
For communication with external digital audio sources, two additional I2S-bus inputs are available. They each have clock, data and Word Select input lines with a maximum useful data length of 18 bits. The external source is master and supplies the clock. The input selection and port selection is controllable via the input selector control register. The DSP program is synchronized with the external source via the Word Select signal. The input allows a variety of clock frequencies, sample frequencies and word lengths.
The DSP program moves data from the two external I2S-bus data output registers to the external processor and reads it back from the two or four external I2S-bus data input registers. The hardware of the bus can be enabled by the input control register. 21
1997 May 30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
To minimise electro magnetic interference (EMI), the output has to be disabled if the output is not used. The timing diagram of the communication is illustrated in Fig.13. 10.5 Relationship between external input and external output
SAA7707H
In this way, it can be performed without interruption of the audio program. The MPX signal from the main tuner of the car radio can be connected to this RDS input via the built-in source selector. The input selection is controlled by the input selector control register. For FM stereo reception, the clock of the total chip is locked to the stereo pilot (19 kHz multiple). For FM mono, the DCS loop keeps the DCS clock around the same 19 kHz multiple. In all other cases, such as AM reception or tape, the DCS circuit has to be set to a preset position. Under these conditions, the RDS system is always clocked by the DCS clock in a 38 kHz (4 x 9.5 kHz) based sequence. 10.8 Timing of clock and data signals
The stereo decoder output has an internal I2S-bus format with 32 clock pulses per channel for 18 valid and 14 zero data bits. Providing that the stereo decoder output is used, the communication with the external processor will also have 32 clock pulses per channel for 18 valid and 14 zero data bits. When an external digital source is selected, the number of valid bits and clock pulses of this source determines the output to the external processor. This relationship is shown in Table 5. Table 5 Relationship between external input and external output. INPUT DATA BITS 18 18 <18 <18 OUTPUT CLOCK BITS 32 as input as input as input OUTPUT DATA BITS 18 18 18 as input
INPUT CLOCK BITS >32 18 and 32 18 and 32 <18 10.6
The timing of the clock and data output is derived from the incoming data signal. Under stable conditions, the data will remain valid for 400 s after the clock transition. The timing of the data change is 100 s before a positive clock change. This timing is suitable for positive and negative triggered interrupts on a microcontroller. The RDS timing is illustrated in Fig.14. During poor reception, it is possible that errors in phase may occur. Consequently the duty cycle of the clock and data signals will vary from a minimum of 0.5 times to a maximum of 1.5 times the standard clock periods. Normally, errors in phase do not occur on a cyclic basis. 10.9 Buffering of RDS data
RDS decoder (RDSCLK and RDSDAT)
The RDS decoder recovers the additional inaudible RDS information transmitted by FM radio broadcasting. The (buffered) data is provided as an output for further processing by a suitable decoder. The operational functions of the decoder are in accordance with EBU specification EN 50067. The RDS decoder has three different functions: 1. Clock and data recovery from the MPX signal 2. Buffering of 16 bits, if selected 3. Interfacing with the microcontroller. 10.7 Clock and data recovery
The repetition frequency of RDS data is approximately 1187 Hz. This results in an interrupt on the microcontroller every 842 s. In a second mode, the RDS interface has a double 16-bit buffer. 10.10 Buffer interface The RDS interface buffers 16 data bits. Each time 16 bits are received, the data line is pulled down and the buffer is overwritten. The control microcontroller has to monitor the input data line at least every 13.5 ms. This mode is selected by the input selector control register. The interface signals from the RDS decoder and the microcontroller in the buffer mode are illustrated in Fig.15. When the buffer is filled with 16 bits, the data line is pulled down. The data line will remain LOW until reading from the buffer is started, by pulling down the clock line. The first data bit is clocked out.
The RDS chain has a separate input. This enables RDS updates during tape play and also the use of a second receiver for monitoring the RDS information of signals from another transmitter (double tuner concept).
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
After 16 clock pulses, the buffer is read and the data line is set HIGH until the buffer is filled again. The microcontroller stops communication by pulling the clock line HIGH. The data is written out just after the clock HIGH-to-LOW transition. The data is valid when the clock is HIGH. When a new 16-bit buffer is filled before the other buffer is read from, that buffer will be overwritten and the old data will be lost. 10.11 DSP reset The reset pin (DSP) is active LOW and has an internal pull-up resistor. To allow a proper switch-on of the supply voltage, a capacitor should be connected between this pin (pin 26) and VSSD. The value of the capacitor is such that the SAA7707H will remain in reset as long as the power supply is not stabilized. A more or less fixed relationship between the DSP reset and the POM (pin 21) time constant is obligatory. The voltage on the POM pin determines the current flowing in the DACs. At 0 V (at pin 21), the DAC currents are zero and therefore the DACs output voltages are also zero. At 5 V, the DAC currents are at their nominal (maximum) value.
SAA7707H
Long before the DAC outputs reach their nominal output voltages, the DSP must be in the working mode (to reset the output register) therefore, the DSP time constant must be shorter than the POM time constant. For advised capacitors, see Figs. 24 and 25. The DSP reset has the following functions: * The bits of the IAC control register are set to logic 0 * The bits of the input selector control register are set to logic 0 * The program counter is set to address $0000. When the level on the DSP is at logic HIGH, the DSP program starts to run. 10.12 Power supply connection and EMC The digital part of the SAA7707H has 5 positive supply lines (VDDD1 to VDDD5) and 10 ground connections (VSSD1 to VSSD10). To minimize radiation, the SAA7707H should be put on a double-layer PCB with, on one side, a large ground plane. The ground supply lines should have a short connection to this ground plane. A coil/capacitor network in the positive supply line can be used as a high frequency filter.
handbook, full pagewidth
Tcy tLC0.35 T SCK tsr0.2 T SD WS thr0 VIH (70%) VIL (20%) tHC0.35 T
VIH (70%) VIL (20%)
SCK
WS
SD
MSB LEFT
MSB RIGHT
MBH173
Fig.12 I2S-bus timing and format.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
tHC
tLC
CL td1
EXSCL
tr tf
tf
tr EXWS
WS
ts2 EXDAT1 EXDAT2 INPUT
td2
EXDAT1 EXDAT2 t3 ta
tr tf
EXDAT OUTPUT
EXDAT
MBH174
Fig.13 Timing diagram of the CDSP to external processor.
handbook, full pagewidth
RDSDAT
RDSCLK
ts
Tcy
tHC
tLC
td
MBH175
Fig.14 RDS timing diagram in direct output mode.
1997 May 30
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Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
RDSDAT
D0
D1
D2
D13
D14
D15
tLC RDSCLK tw block ready tHC Tcy start reading data
MBH176
Fig.15 Interface signals RDS decoder and microcontroller.
11 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDDD VDDD IIK IOK IO IDDD ISSD LTCH Po Ptot Tamb Tstg VESD PARAMETER DC supply voltage voltage difference between any two VDDX pins DC input clamp diode current DC output clamp diode current DC output sink or source current DC supply current per pin DC ground supply current per pin latch-up protection power dissipation per output total power dissipation operating ambient temperature storage temperature electrostatic handling for all pins note 1 note 2 Notes 1. Human body model: C = 100 pF; R = 1500 ; 3 pulses positive plus 3 pulses negative. 2. Machine model: C = 200 pF; L = 2.5 H; R = 25 ; 3 pulses positive plus 3 pulses negative. 1997 May 30 25 CIC specification/test method VI < -0.5 V or VI > VDDD + 0.5 V output type 4 mA; VO < -0.5 V or VO > VDDD + 0.5 V output type 4 mA; -0.5 V < VO < VDDD + 0.5 V CONDITIONS - - - - - - 100 - - -40 -65 3000 300 MIN. -0.5 MAX. +6.5 550 10 20 20 50 50 - 100 1600 +85 +150 - - V mV mA mA mA mA mA mA mW mW C C V V UNIT
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
12 THERMAL CHARACTERISTICS SYMBOL Rth j-a Rth j-a PARAMETER from junction to ambient in free air and VSSD lead fingers 50, 51, 54 and 55 of the QFP80 soldered to a PCB copper plate of 36 cm2 from junction to ambient in free air and VSSD lead fingers 50, 51, 54 and 55 of the QFP80 not connected to a PCB copper plate
SAA7707H
VALUE 35 42
UNIT K/W K/W
13 DC CHARACTERISTICS VDDD = 4.75 to 5.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Digital part DIGITAL INPUTS AND OUTPUTS; NOTE 1 VDDD(tot) IDDD(tot) total DC supply voltage total DC supply current all VDDD pins maximum activity of the DSP; fxtal = 36 MHz maximum activity of the DSP; fxtal = 36 MHz 4.75 - 5.0 160 5.5 200 V mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Ptot
total power dissipation
-
0.8
1.1
W
VIH
HIGH level input voltage; pins 23 to 25, 27, 28, 30 to 33, 38 to 40, 44 to 48, 60 and 62 HIGH level input voltage; pin 26
0.7VDDD
-
-
V
0.8VDDD -
- -
- 0.2VDDD
V V
VIL
LOW level input voltage; pins 23 to 28, 30 to 33, 38 to 40, 44 to 48, 60 and 62 hysteresis voltage pin 26 HIGH level output voltage; pins 23, 35 to 37, 42, 43, 48, 57, 60 and 61 LOW level output voltage; pins 23, 35 to 37, 39, 42, 43, 48, 57, 60 and 61 input leakage current; pins 24, 25, 27, 28, 38 and 44 to 47 VDDD = 4.75 V; IO = -4 mA
Vhys VOH
- 4.25
0.33VDDD - - -
V V
VOL
VDDD = 4.75 V; IO = 4 mA
-
-
0.5
V
ILI
VI = 0 or VDDD
-
-
1
A
IOZ
3-state output leakage VO = 0 or VDDD current; pins 23, 35 to 37, 39, 42, 48, 57 and 60
-
-
5
A
1997 May 30
26
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL Rpu Rpd
PARAMETER internal pull-up resistor to VDDD pin 26 internal pull-down resistor to VSSD pins 30 to 33, 40 and 62 input rise time input fall time output rise time for LOW-to-HIGH transition
CONDITIONS 17 Vi = VDDD 17
MIN. - -
TYP. 134 134
MAX.
UNIT k k
tr tf tr
VDDD = 5.5 V VDDD = 5.5 V
- -
6 6 -
200 200 1.43 + 0.24CL
ns ns ns
VDDD = 4.75 V; - Tamb = 85 C; pins 23, 48 and 60 VDDD = 4.75 V; Tamb = 85 C; pins 43 and 61 VDDD = 4.75 V; Tamb = 85 C; pins 35 to 37, 42 and 57 -
-
4.75 + 0.28CL
ns
-
-
4.75 + 0.28CL
ns
VDDD = 5.5 V; 0.351 + 0.097CL - Tamb = -40 C; pins 23, 48 and 60 VDDD = 5.5 V; Tamb = -40 C; pins 43 and 61 VDDD = 5.5 V; Tamb = -40 C; pins 35 to 37, 42 and 57 tf output fall time for HIGH-to-LOW transition 1.302 + 0.101CL -
-
ns
-
ns
1.302 + 0.101CL -
-
ns
VDDD = 4.75 V; - Tamb = 85 C; pins 23, 48 and 60 VDDD = 4.75 V; Tamb = 85 C; pins 43 and 61 VDDD = 4.75 V; Tamb = 85 C; pins 35 to 37, 42 and 57 -
-
1.82 + 0.31CL
ns
-
6.44 + 0.36CL
ns
-
-
6.44 + 0.36CL
ns
0.386 + 0.097CL - VDDD = 5.5 V; Tamb = -40 C; pins 23, 48 and 60 VDDD = 5.5 V; Tamb = -40 C; pins 43 and 61 VDDD = 5.5 V; Tamb = -40 C; pins 35 to 37, 42 and 57 1997 May 30 27 0.971 + 0.115CL -
-
ns
-
ns
0.971 + 0.115CL
-
-
ns
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL Analog part
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
ANALOG INPUTS: VDDA1 = 5 V; Tamb = 25 C VDDA1 VrefMPX analog supply voltage for ADC common mode reference voltage MPX ADC pin 70 common mode reference voltage RDS ADC pin 80 output impedance at pins 70 and 80 positive reference voltage for MPX ADC and RDS ADC positive reference current for MPX ADC negative reference voltage for MPX ADC and RDS ADC negative reference current MPX ADC negative reference voltage level A/D negative reference current for level ADC input offset voltage MPX input offset voltage RDS with respect to pins 68 and 69 with respect to pins 68 and 69 4.75 0.47VDDA1 5.0 5.5 V V
0.5VDDA1 0.53VDDA1
VrefRDS
0.47VDDA1
0.5VDDA1 0.53VDDA1
V
ZO VDACPM
- 4.75
600 5.0
- 5.5
V
IVDACPM VDACNM
- -0.3
-20 0
- +0.3
A V
IVDACNM VDACNL IVDACNL VIosMPX VIosRDS VDDD1
- -0.3 - - - 4.75
20 0 5 140 140
- +0.3 - - - 5.5
A V A mV mV
ANALOG OUTPUTS: VDDD = VDDA = VDDO = 5 V; Tamb = 25 C digital supply voltage for upsample filter and digital DAC analog supply voltage for DAC operational amplifier supply voltage input voltage on pin 20 impedance between pins 15 and 20 impedance between pins 14 and 20 input voltage on pin 13 with respect to pins 14 and 15 with respect to pins 14 and 15 5.0 V
VDDA1 VDDO Vref Z15-20 Z14-20 V13
4.75 4.75 0.47VDDO 12 12 0.46VDDA
5.0 5.0 0.5VDDO 18 18 0.5VDDA
5.5 5.5 0.53VDDO 25 25 0.54VDDA
V V V k k V
1997 May 30
28
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL IO(DAC; max)
PARAMETER maximum output current from DACs
CONDITIONS reference resistance to pin 14 = 18 k 490
MIN.
TYP. 570 650
MAX.
UNIT A
VO(os) VO(rms)
DC offset voltage at DAC with respect to output pin 20 AC output voltage of operational amplifier outputs at maximum signal pins 10, 12, 17 and 19 (RMS value) average DC output voltage at pins 10, 12, 17 and 19 pull-up resistor to pin 15 RL > 5 k; Rfb = 2.7 k; note 2
- 0.94
5 1.09
- 1.24
mV V
VO(av)
RL > 5 k; Rfb = 2.7 k; note 2
2.25
2.5
2.75
V
RPOM
64
128
260
k
Crystal oscillator: Tamb = 25 C VDD(osc) oscillator supply voltage 4.75 - - no load - 5.0 5.5 V A mA mA Current per supply pin or pin group: Tamb = 25 C; VDD = 5 V (typ.); 5.5 V (max.) IDDD1 IDDA IDDO digital supply current DACs pin 7 analog supply current DAC pin 8 supply current for operational amplifiers pin 15 supply current for digital circuitry and periphery pins 49, 52, 53 and 56 supply current for crystal circuit pin 65 supply current for ADCs pin 69 20 4 2 50 8 4
IDDD
-
137.5
165
mA
IDDX IDDA1 Notes
- -
1.5 15
3 20
mA mA
1. The values for the capitative load CL are given in pF. 2. RL is the AC impedance of the external circuitry at 1 kHz, connected to the audio outputs in the application. There is also no DC current flowing through RL.
1997 May 30
29
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
14 AC CHARACTERISTICS SYMBOL PARAMETER CONDITIONS MIN. TYP.
SAA7707H
MAX.
UNIT
Analog DC inputs (LEVEL-FM, AM): VDDD = VDDA1 = 5 V; Tamb = 25 C S/N signal-to-noise ratio ADC RMS value; not weighted; B = 0 to 29 kHz; maximum input RMS value; not weighted; audio mode; B = 0 to 19 kHz; maximum input Ri VFS VI(os) ViADR fco fsr input resistance full-scale input voltage DC offset voltage at minimum input voltage input voltage level decimation filter attenuation pass-band cut-off frequency at -3 dB sample rate after decimation radio mode audio mode THD < 1% VDDA1 = 4.75 to 5.5 V with respect to VDACNL Rext = 5 k 48 54 - dB
52
58
-
dB
200 - -0.3 20 - - -
400 - - - 29 38 38 - 60 -71 0.03 85
- 60 +7.5 - - 76 76 - 72 -61 0.09 -
k mV V dB/Dec kHz kHz kHz
1.05VDDA1 1.1VDDA1
1.15VDDA1 V
Analog AC inputs: pins MPX, AM, TAPE and AUX Vi(con, rms) Ri THD S/NADC maximum conversion input voltage level (RMS value) input resistance total harmonic distortion signal-to-noise ratio for ADC fi = 1 kHz; Vi = 1 V (RMS) fi = 1 kHz; Vi = 1 V (RMS) not multiplexed; B = 19 kHz; Vi = 1 V (RMS) multiplexed; unweighted; B = 19 kHz; Vi = 1 V (RMS) S/NAM signal-to-noise ratio for AM B = 5 kHz; Vi = 200 mV (RMS); (M = 30%) Vi = 200 mV (RMS); (f = 22.5 kHz); B = 19 kHz; unweighted; (M = 30%) Vi = 200 mV (RMS); (f = 22.5 kHz); B = 19 kHz; unweighted; (M = 30%) 1.1 48 - - 81 V k dB % dB
72
76
-
dB
68
72
-
dB
S/NFM(mon)
signal-to-noise-ratio for FM mono
69
72
-
dB
S/NFM(st)
signal-to-noise-ratio for FM stereo
60
63
-
dB
1997 May 30
30
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL S/NTAPE
PARAMETER signal-to-noise-ratio for TAPE (+10 kHz RC) signal-to-noise-ratio for AUX
CONDITIONS B = 19 kHz; Vi = 1 V (RMS); unweighted B = 19 kHz; Vi = 1 V (RMS); unweighted 70
MIN. 74
TYP. -
MAX.
UNIT dB
S/NAUX
72
76
-
dB
19
carrier and harmonic pilot signal fi = 19 kHz suppression at the output no modulation with and without modulation (for 19 kHz including notch) carrier and harmonic subcarrier; fi = 38 kHz suppression at the output no modulation with and without modulation carrier and harmonic subcarrier; fi = 57 kHz suppression at the output no modulation with and without modulation carrier and harmonic subcarrier; fi = 76 kHz suppression at the output no modulation with and without modulation intermodulation intermodulation traffic radio suppression subsidiary communication authority (SCA) adjacent channel interference adjacent channel interference pilot threshold voltage at pin 42 hysteresis level of pilot voltage input frequency range MPX -3 dB; ADC via bitstream test output FM stereo channel separation audio frequency response FM channel unbalance left/right TAPE, AUX, FM and AM fi = 1 kHz fi = 10 kHz at -3 dB via DSP at DAC output fmod = 10 kHz; fspur = 1 kHz; note 1 fmod = 13 kHz; fspur = 1 kHz; note 1 fi = 57 kHz; note 2 fi = 67 kHz; note 3 fi = 114 kHz; note 4 fi = 190 kHz; note 4 stereo ON stereo OFF
- - - - - - - - 77 76 - - - - - - - 0 40 25 16 -
81 98
- - - - - - - - - - - - - - - - - 55 - - - 0.5
dB dB
38
83 91 83 96 84 94 - - 110 110 110 110 35.6 35.5 0 - 45 30 - -
dB dB dB dB dB dB dB dB dB dB dB dB mV mV dB kHz dB dB kHz dB
57
76
IM10 IM3 57(VF) 67 114 190 Vpilot(rms) HYS fi cs fresFM |Gv|
1997 May 30
31
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL cs
PARAMETER channel separation TAPE and AUX
CONDITIONS fi = 1 kHz fi = 10 kHz fi = 1 kHz, software compensated 40 25 - 18 65 50 35 I2S-bus;
MIN. 45 30 50 - - - 45
TYP. - - - - - - -
MAX.
UNIT dB dB dB kHz dB dB dB
fres ct PSRR
frequency response TAPE and AUX crosstalk between inputs power supply ripple rejection for MPX and RDS ADCs
at -3 dB fi = 1 kHz fi = 15 kHz output via ADC input shorted; fripple = 1 kHz; Vripple = 100 mV (peak); CVrefMPX = 22 F; CVrefRDS = 22 F; CVDACPM = 10 F output via DAC; ADC input shorted; fripple = 1 kHz; Vripple = 100 mV (peak); CVrefRDS = 22 F THD < 1%
power supply ripple rejection for ADC level
29
39
-
dB
Analog AC inputs: RDS Vi(rms) Ri pilot mux fosc input voltage level (RMS value) input resistance RDS ADC pilot attenuation RDS nearby selectivity RDS multiplex attenuation RDS allowable frequency deviation 57 kHz RDS
=5
1.1 48 50
- 60 - - - - -
- 72 - - - - 6
V k dB dB dB dB Hz
neighbouring channel at 200 kHz distance mono stereo maximum crystal deviation of 100 ppm V; Tamb = 25 C input via I2S-bus; fripple = 1 kHz; Vripple = 100 mV (peak); CVref = 22 F with respect to the average of the 4 outputs; tolerance Ro < 0.1%; full-scale output two outputs digital silence other two maximum volume; faudio = 10 kHz
61 70 40 -
Analog outputs: VDDD = VDDA = VDDO PSRR power supply ripple rejection DACs
35
42
-
dB
Vo(DAC)
maximum deviation in output level (plus or minus) of the 4 DAC current outputs crosstalk between all outputs in the audio band DC open loop gain of operational amplifiers
-
-
0.38
dB
ct
-
-
-60
dB
GO
-
85
-
dB
1997 May 30
32
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL Zo fug Io(sc) RES
PARAMETER AC output impedance of operational amplifiers unity gain frequency operational amplifiers short-circuit current output DAC resolution
CONDITIONS RL > 5 k; note 5 open loop output short-circuited to ground fi = 1 kHz; Vo = 2.8 V (p-p) (full-scale) fi = 1 kHz; at -60 dB; A-weighted Vref(o) = 4.46 V (p-p); fi = 1 kHz; at -60 dB; A-weighted Vref(o) = 4.46 V (p-p); fi = 20 Hz to 17 kHz; A-weighted RMS value; B = 20 kHz, A-weighted fi = 60 Hz and 7 kHz; ratio 4 : 1 fxtal = 36.9 MHz fs = fs - 3 dB - - - - -
MIN.
TYP. 1.5 4.5 10 18 -70 - -
MAX.
UNIT MHz mA bits dB
25 - -60
(THD + N)/S DAC total harmonic distortion plus noise-to-signal ratio of DAC and operational amplifiers DR dynamic range
- 92
-38 102
-28 -
dBA dBA
DS
digital silence
-
-110
-100
dBA
digital silence noise level at output IM fs(max) B CL RL intermodulation distortion/comparator maximum sample frequency bandwidth of DAC allowed load capacitance on DAC voltage outputs allowed load resistor on DAC voltage outputs
- - 48 - - 2
5 -70 -
1 2fs
15 -55 - - 2.5 -
V dB kHz kHz nF k
- -
Crystal oscillator at: VDDX = 5 V; Tamb = 25 C fxtal f I64 Gm Vxtal CL Rxtal crystal frequency spurious frequency attenuation output current pin 64 transconductance voltage across crystal load capacitance allowed resistance loss of crystal note 6 Cp = 5 pF; Cx1 = 10 pF; Cx2 = 10 pF at start-up - 20 - 4 - - - 36.860 - - 8 500 10 20 - - 1 - - - 100 MHz dB mA mS mV pF
1997 May 30
33
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Timing at: VDDD = VDDA = VDDA1 = VDDX = 5 V; Tamb = 25 C fxtal fxtal/fxtal fxtal/T fi(max) crystal frequency frequency adjustment tolerance drift over temperature range maximum input frequency of I2C-bus clock - -30 -30 100 36.860 - - - - +30 +30 - MHz ppm ppm kHz
I2S-bus inputs and outputs (see Fig.18) tr rise time VDDD = 4.75 V; Tamb = 85 C VDDD = 5.5 V; Tamb = -40 C tf fall time VDDD = 4.75 V; Tamb = 85 C VDDD = 5.5 V; Tamb = -40 C tHC tLC tdWS th ts td ta fclk ts Tcy tHC tLC th tw tpb tHC tLC Other fEXCLK input frequency on pin 40 - - 22 MHz clock output HIGH time clock output LOW time Word Select delay time data hold time data set-up time data delay time data out access time - 1.302 + 0.101CL - 0.971 + 0.115CL 112 112 0 0 25 0 - - 100 - 220 220 100 1 2 1 1 - - - - - - - - - - - 4.75 + 0.28CL - 6.44 + 0.36CL - - - - - - 5 5 + 0.5CL - - - 640 640 - - - - - ns ns ns ns ns ns ns ns ns ns ns
RDS; (see Figs.14 and 15) nominal clock frequency clock set-up time periodic time clock HIGH time clock LOW time data hold time wait time periodic time clock HIGH time clock LOW time RDS-clock 1187.5 - 842 - - - - - - - Hz s s s s s s s s s
1997 May 30
34
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
Notes to the AC characteristics 1. Intermodulation suppression (BFC: Beat Frequency Components). a) 2 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz); fs = (2 x 10 kHz) - 19 kHz. b) 3 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz); fs = (3 x 13 kHz) - 38 kHz. c) Measured with 91% mono signal; fmod = 10 or 13 kHz; 9% pilot signal. 2. Traffic radio (VF) suppression. a) 57(VF) = Vo(signal) (at 1 kHz)/Vo(spurious) (at 1 kHz 23 Hz). b) Measured with 91% stereo signal; fmod = 1 kHz; 9% pilot signal. c) 5% traffic subcarrier (f = 57 kHz; fmod = 23 Hz AM, m = 0.6). 3. SCA (Subsidiary Communication Authorization). a) 67 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 9 kHz); fs = (2 x 38 kHz) - 67 kHz. b) Measured with 81% mono signal; fmod = 1 kHz; 9% pilot signal. c) 10% SCA subcarrier (fs = 67 kHz, unmodulated). 4. ACI (Adjacent Channel Interference). a) 114 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 4 kHz); fs = 110 kHz - (3 x 38 kHz). b) 190 = Vo(signal) (at 1 kHz)/Vo(spurious) (at 4 kHz); fs = 186 kHz - (5 x 38 kHz).
SAA7707H
c) Measured with 90% mono signal; fmod = 1 kHz; 9% pilot signal; 1% spurious signal (fs = 110 kHz or 186 kHz, unmodulated). 5. RL is the AC impedance of the external circuitry at 1 kHz connected to the audio outputs in the application. There is also no DC current flowing through RL. 6. The load capacitance is the sum of the series connection of C x 1 and C x 2 (see Fig.11) and the parasitic parallel capacitor of the crystal Cp.
1997 May 30
35
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
15 I2C-BUS CONTROL AND COMMANDS 15.1 Characteristics of the I2C-bus
SAA7707H
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to VDDD via a pull-up resistor when connected to the output stages of a microcontroller. Data transfer can only be initiated when the bus is not busy. 15.2 Bit transfer
acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH, to enable the master to generate a STOP condition (see Fig.19). 15.6 15.6.1 I2C-bus format ADDRESSING
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse, as changes in the data line at this time will be interpreted as control signals. The maximum clock frequency is 100 kHz (see Fig.16). 15.3 START and STOP conditions
Before any data is transmitted on the I2C-bus, the device that should respond is addressed first. The addressing is always done with the first byte transmitted after the START procedure. 15.6.2 SLAVE ADDRESS (A0 PIN)
The CDSP acts as a slave receiver or slave transmitter. Therefore, the clock signal SCL is only an input signal. The data signal SDA is a bi-directional line. The CDSP slave address is shown in Table 6. Table 6 MSB 0 0 1 1 1 0 A0 Slave address LSB R/W
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Fig.17). 15.4 Data transfer
A device generating a message is a `transmitter', a device receiving a message is the `receiver'. The device that controls the message is the `master' and the devices that are controlled by the master are the `slaves' (see Fig.18). 15.5 Acknowledge
The sub-address bit A0 corresponds to the hardware address pin A0, which allows the device to have 1 of 2 different addresses. The A0 input is also used in test mode as a serial input of the test control block. 15.6.3 CDSP WRITE CYCLES
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge-related clock pulse. A slave receiver that is addressed must generate an acknowledge after the reception of each byte. Also, a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge-related clock pulse. Set-up and hold times must be taken into account. A master receiver must signal an end-of-data to the transmitter by not generating an 1997 May 30 36
The I2C-bus configuration for a WRITE cycle is illustrated in Fig.22. The WRITE cycle is used to write in the IAC register, the input selector control register and to initialize or update coefficient values in XRAM or YRAM. The data is transferred from the I2C-bus register to the DSP register once every DSP cycle. The I2C-bus interface circuitry in the SAA7707H requires that the LOW period of the SCL line following the acknowledge bit is at least 1/fs (in seconds); where fs is the audio sampling frequency (in Hertz). This requirement must be met for a single write operation and an auto-incremental operation, but only applies to the acknowledge bit following each DATA-L (see Figs 20 and 21). The data length is 2 or 3 bytes, depending on the accessed memory. If the Y-memory is addressed the data length is 2 bytes, If the X-memory is addressed the length is 3 bytes. The slave receiver detects the address and adjusts the byte length accordingly.
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
15.6.4 CDSP READ CYCLES
SAA7707H
The configuration for a READ cycle is illustrated in Fig.23. The READ cycle is used to read data values from XRAM or YRAM. The data is transferred from the DSP register to the I2C-bus register at execution of the MPI instruction in the DSP program. Therefore, an MPI instruction should be added at least once every DSP cycle.
I2C-bus
th
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.16 Bit transfer on the I2C-bus.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.17 START and STOP conditions.
1997 May 30
37
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
SDA MSB acknowledgement signal from receiver byte complete; interrupt within receiver clock line held low while interrupts are serviced SCL S START CONDITION acknowledgement signal from receiver
1
2
7
8
9 ACK
1
2
3-8
9 ACK
MBH177
P STOP CONDITION
Fig.18 Data transfer on the I2C-bus.
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START CONDITION
MBH178
1
2
8
9
clock pulse for acknowledgement
Fig.19 Acknowledge on the I2C-bus.
1997 May 30
38
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidth
SDA
SCL
1-7
8
9
1-7
8
9
1-7
8
9 P
DATA-H
ACK
DATA-M
ACK
DATA-L
ACK 1/fs
STOP condition
MGK426
minimum required LOW period
Fig.20 Minimum required SCL LOW period; single write.
1997 May 30
39
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k, full pagewidth
1997 May 30
SDA SCL 1-7 8 9 1-7 8 9 1-7 8 9 DATA-H ACK DATA-M ACK DATA-L ACK
Philips Semiconductors
Car radio Digital Signal Processor (CDSP)
1-7
8
9
1-7
8
9
1-7
8
9
DATA-H 1/fs
ACK
DATA-M
ACK
DATA-L
ACK
MGK427
40
minimum required LOW period
Preliminary specification
SAA7707H
Fig.21 Minimum required SCL LOW period; auto-incremental write.
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A
Philips Semiconductors
Car radio Digital Signal Processor (CDSP)
S00111000C
K
ADDR H
A C K
ADDR L
A C K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W
MGD568
Fig.22 Master transmitter writes to CDSP registers.
41
A
S00111000C
K
ADDR H
A C K
ADDR L
A A CS00111001C K K
DATA H
A C K
DATA M
A C K
DATA L
A CP K
auto increment if repeated n-groups of 3 (2) bytes address R/W R/W
MGA808 - 1
Fig.23 Master transmitter reads from CDSP registers.
16 SOFTWARE DESCRIPTION A detailed description of the software feature, complete with operating instructions, is provided in the application manual.
Preliminary specification
SAA7707H
17 APPLICATION INFORMATION The application diagram illustrated in Figs. 24 and 25 must be considered as one of the examples of a (limited) application of the SAA7707H. For example, in the application shown, the I2S-bus inputs of the DCC and CD are not used.
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
handbook, full pagewidthV +5
10 H C1 4.7 F L1 +5 V 220 H L3 C3 100 nF C21 100 nF C20 1 nF 2 CINT 1 VDACNL 67 VSSG 68 VSSA1 69 VDDA1 5 VSSD1 22 VSSD2 50 VSSD3 51 VSSD4 54 VSSD5 55 VSSD6 34 VSSD7 41 VSSD8 29 VSSD9 66 CDCLK 23 VSSX 63 R13 100 nF BLM21A10 L4 R12 100 +5 V (e.g.) L5 4.7 H C25 4.7 nF 100 k X1 36.86 MHz C27 10 pF +5 V
+5 V
BLM21A10 L2 C2 100 F
+5 V
R1 1 k C4 10 F C5 22 F
77 78 70
VDACPM VDACNM VrefMPX VrefRDS MPXRDS AM FM AUXR AUXL TAPER AUXR AMAF FMMPX
C6 R2 4.7 k C7 R3 1 nF
80 62 4 3 72 71 74 72 75
22 F
LEVEL (AM, FM) C14 CDIN-R
470 nF 4.7 k C8 C15 R4 CDIN-L 470 nF 4.7 k C9 C16 R5 CASS-R 470 nF 4.7 k C10 C17 R6 CASS-L 470 nF 4.7 k C11 R7 RADIO-F (AM) 3.3 k C12 R7 MPX (FM) 3.3 k C13
330 pF
SAA7707H
330 pF
3.3 nF
3.3 nF C18 330 pF 150 pF
220 nF
76 79 1 F
RDSDAT
RDSCLK
FMRDS SHTCB TSCAN RTCB
XTALO
C19
32
33
30
60 R9 100 R11 100 220 pF
61 C24
65
64
C22 220 pF
C23 R10 100
RDSCLK
RDSDAT
C26 10 pF
MBH179
Fig.24 Application diagram (continued in Fig.25).
1997 May 30
42
XTALI
VDDX
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
SAA7707H
BLM32A07 book, full pagewidth +5 V L6 C33 100 pF C32 100 F
RDSMUTE
PAUSE
+5 V D1 BAT54 C34 100 pF C36 22 F C35 100 nF
C31 100 nF
R16 220
R17 220
56 VDDD2
49 VDDD3
52 VDDD4
53 VDDD5
44 MUTE
45 DEEM
42 STEREO
43 MSS/P
7 VDDD1
8 VDDA
15 VDDO
14 VSSO
6 VSSA POM FIOL FVOL 21 18 19 R18 2.7 K C38 2.2 nF R23 100 FIOR FVOR 16 17 C39 2.2 nF R24 100 RIOL 11 12 R20 2.7 K C40 2.2 nF R25 100 RIOR RVOR EXCLK Vref DSPRESET 9 10 40 20 R21 2.7 K C41 2.2 nF R26 100 C37 4.7 F C44 2.2 F
MICROCONTROLLER
FRONT-LEFT C43 10 nF C46 2.2 F FRONT-RIGHT C45 10 nF C48 2.2 F REAR-LEFT C47 10 nF C50 2.2 F REAR-RIGHT C49 10 nF
R19 2.7 K
SAA7707H
RVOL
DCCDAT
DCCCLK
Iref(int) 13 R22 18 k C42 22 F
EXDAT2
EXDAT1
VSSD10
DCCWS
CDDAT
EXDAT
EXSCL
TEST2
TEST1
DCWS
EXWS
SDA
SCL
A0 31
24
25
48
47
46
59
57
58
35
36
28
27
37
38
39
26 C30 220 nF
R14 220 C28 100 pF
R15 220
C29 100 pF SCL SDA
MBH180
Fig.25 Application diagram (continued from Fig.24).
1997 May 30
43
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
18 PACKAGE OUTLINE QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm
SAA7707H
SOT318-2
c
y X
64 65
41 40 ZE
A
e E HE wM pin 1 index bp 25 1 wM D HD ZD B vM B 24 vMA Lp L detail X A A2 A1 (A 3)
80
e
bp
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 3.2 A1 0.25 0.05 A2 2.90 2.65 A3 0.25 bp 0.45 0.30 c 0.25 0.14 D (1) 20.1 19.9 E (1) 14.1 13.9 e 0.8 HD 24.2 23.6 HE 18.2 17.6 L 1.95 Lp 1.0 0.6 v 0.2 w 0.2 y 0.1 Z D (1) Z E (1) 1.0 0.6 1.2 0.8 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT318-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-08-01
1997 May 30
44
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
19 SOLDERING 19.1 Introduction 19.3 Wave soldering
SAA7707H
There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). 19.2 Reflow soldering
Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering cannot be avoided, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 19.4 Repairing soldered joints
Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9397 750 00192). Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C.
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 May 30
45
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
20 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
SAA7707H
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 21 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 22 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1997 May 30
46
Philips Semiconductors
Preliminary specification
Car radio Digital Signal Processor (CDSP)
NOTES
SAA7707H
1997 May 30
47
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 1 60 101, Fax. +43 1 60 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 4 Rue du Port-aux-Vins, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Shivsagar Estate, A Block, Dr. Annie Besant Rd. Worli, MUMBAI 400 018, Tel. +91 22 4938 541, Fax. +91 22 4938 722 Indonesia: see Singapore Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Rua do Rocio 220, 5th floor, Suite 51, 04552-903 Sao Paulo, SAO PAULO - SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 829 1849 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 3 301 6312, Fax. +34 3 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 632 2000, Fax. +46 8 632 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2686, Fax. +41 1 481 7730 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777
For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA54
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547027/1200/02/pp48
Date of release: 1997 May 30
Document order number:
9397 750 02261

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